A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET

Kyoung-Jun Moon,Dong-Ryeol Oh,Young-Hyo Park,Kyung-Hoon Lee, Sun-Jae Park,Sung-No Lee, Hee-Chang Hwang,Hyo-Chul Shin,Young-Jae Cho,Michael Choi,Jong-Shin Shin

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2022）

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摘要

A 12b 10GS/s 16-channel time-interleaved (TI) ADC with cascaded input buffers, 625MS/s voltage-current (V-I) pipelined SAR ADCs and a digital processing timing-skew background calibration is proposed. A prototype 10GS/s TI ADC in 5nm FinFET achieves 48dB SNDR at the Nyquist input with 625mW power consumption, leading to a FoM Walden of 305fJ/c-s.

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关键词

Nyquist input,SNDR,V-I pipelined SAR ADC,voltage-current pipelined SAR ADC,TI ADC,cascaded input buffers,digital processing timing-skew background calibration,16-channel time-interleaved ADC,FinFET,size 5.0 nm,noise figure 48.0 dB,power 625.0 mW,word length 12 bit

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