A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM

Ji-Young Kim, Taeryeong Kim,Jeonghyeok You,Kiryong Kim,Byoung Mo Moon,Kyomin Sohn,Seong-Ook Jung

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2022）

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摘要

A low power through-silicon via (TSV) I/O for the high-bandwidth memory is proposed with a 65nm CMOS process. The proposed TSV I/O, which employs a low-supply voltage for low-power operation, consists of a 4-to-1 multiplexer (MUX) with replica MUX, pre-driver that realizes pre-emphasis without static power consumption, and digitally calibrated 1-to-4 de-MUX comparator. The measured energy efficiency is 0.179-0.185pJ/b/pF with a PRBS-31 at 5-10Gb/s.

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关键词

CMOS process,low power through-silicon via,low power TSV I/O,de-MUX comparator,static power consumption,pre-driver,replica MUX,4-to-1 multiplexer,low-power operation,low-supply voltage,high-bandwidth memory,low power through-silicon,next generation HBM,size 65.0 nm,bit rate 5 Gbit/s to 10 Gbit/s

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