Study on Process Improvement and Yield Enhancement of 40Nm E-Flash AIO Wet Strip

40nm e- flash product CP 1 test results show that the wafer has a special map, and the yield is lower. The WAT data shows that Rc is very large, indicating that the chip circuit is open. Through step by step process check and PF A analysis, the root cause of yield loss is copper loss at the bottom of the Via in AIO loop. After AIO Wet Strip, the residual acid in Via will continue to etch copper at the bottom and form serious under cut, resulting in poor connection at the bottom, thus resulting in loss of yield. In this paper, by optimizing the wet cleaning process, a thin passivation layer is formed on the copper surface to avoid further erosion of copper by residual acid and prevent the formation of defects. The results show that this method greatly improves product yield and process reliability.