Investigating the Effect of different eFPGAs fabrics on Logic Locking through HW Redaction

Most VLSI design companies are now fabless. This implies that they need to rely on third party fabs to fabricate their Integrated Circuits (ICs). Because these fabs are often located in geographical different locations it is important to have mechanisms in place to protect these companies against Intellectual Property (IP) theft. One approach that has become very popular due to its relative simplicity and practicality is logic locking. One of the problems with traditional locking mechanisms is that the locking circuitry is built into the netlist that the VLSI design company delivers to the foundry which has now access to the entire design including the locking mechanism. This implies that they could potentially tamper with this circuitry or reverse engineer it to obtain the locking key. One relatively new approach that has been coined logic locking through omission, or hardware redaction, maps a portion of the design to an embedded FPGA (eFPGA). The bitstream of the eFPGA now acts as the locking key. This new approach has been shown to be more secure as the foundry has no access to the bitstream during the manufacturing stage. The obvious drawbacks are the increase in design complexity and the area and performance overheads associated with the eFPGA. In this work investigate the tradeoffs of mapping different portions of behavioral descriptions for High-Level Synthesis using two different eFPGA fabrics and show that it is important to choose the eFPGA fabric based on the characteristic of the design to be locked.