A High-Resolution High-Linearity Three-Step Hybrid Time-to-Digital Converter in 40-nm CMOS

Biao Zhang,Xuefei Bai, Zhe Yang

2021 IEEE International Workshop on Electromagnetics: Applications and Student Innovation Competition (iWEM)（2021）

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摘要

In this paper, a high-resolution high-linearity three-step TDC design in 40-nm CMOS technology is presented. The coarse step was designed based on a counter to achieve a wide range. The medium step was designed based on a multi-phase clock interpolation structure with DLL to improve the linearity. The fine step was designed based on a vernier structure with ring oscillators to achieve high resolution. The simulation results show that the design has a 5-ps resolution and a 2-μs range. The DNL is in (−0.2, 0.65) LSB, and the INL is in (−0.9, 0.38) LSB.

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关键词

time-to-digital converter,three-step TDC design,CMOS technology,multiphase clock interpolation structure,high-resolution high-linearity three-step hybrid time-to-digital converter,ring oscillators,Vernier structure,size 40 nm,time 5 ps,time 2 mus

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