Understanding and modelling the PBTI reliability of thin-film IGZO transistors
2021 IEEE International Electron Devices Meeting (IEDM)(2021)
摘要
We study the impact of the gate-dielectric on the Positive Bias Temperature Instability (PBTI) of IGZO thin-film transistors (TFT). We show that PBTI is controlled by the gate-dielectric pre-existent electron traps and its hydrogen content. The degradation process can be composed of up to four different mechanisms with different time kinetics, voltage acceleration factors and activation energies. A simplified physics-based model is used to reproduce stress and relaxation traces recorded in a wide range of test conditions. Gate-dielectric optimization enables scaled EOT (2.5nm) IGZO TFT to achieve a record lifetime of ~ 1 year continuous operation at 95°C and
$\mathrm{V}_{\text{ov}}=1\mathrm{V}$
, with a strict failure criterion of
$\vert \Delta \mathrm{V}_{\text{th}}\vert < 30\text{mV}$
.
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关键词
gate-dielectric optimization,PBTI reliability,thin-film IGZO transistors,Positive Bias Temperature Instability,IGZO thin-film transistors,TFT,gate-dielectric pre-existent electron traps,hydrogen content,degradation process,time kinetics,voltage acceleration factors,activation energies,simplified physics-based model,relaxation traces,temperature 95.0 degC,size 2.5 nm,voltage 1.0 V
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