A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces

In massively parallel short-reach (SR) interfaces [2]–[5], thousands of I/Os communicate through many low-loss parallel interconnects (Fig. 28.7.1). Due to the large number of I/Os, each transceiver (TRX) design must fit within a small area and be energy-efficient. One challenge in TRX design is the increasing clocking area and power. Distributing the clock to thousands I/Os, while satisfying stringent duty cycle constraints, requires many duty-cycle correction (DCC) and duty-cycle detection (DCD) circuits. For reliable data recovery with a reduced eye opening, RXs also require precise clock and data recovery (CDR) or clock and data alignment (CDA) circuits. Their area and power also needs to be minimized, as these circuits are employed in proportion to the I/O count.