OPAL: On-the-go Physical Attack Lab to Evaluate Power Side-channel Vulnerabilities on FPGAs

Power side-channel attacks on intellectual property blocks (IP) are prevalent in a wide spectrum of computing platforms ranging from smartphones to large-scale servers. However, the existing frameworks to evaluate such attacks require physical access to the designs. In addition, they are limited by their cost and inability to scale well. They rely on external devices to monitor and modify physical operating conditions of a target system. Furthermore, their operation and deployment require deep electrical engineering expertise such as making board-level modifications. This work introduces On-the-go Physical Attack Lab (OPAL), which is a hardware/software framework to evaluate power side-channel information leakage of a hardware design on FPGAs. OPAL leverages on-chip components available in most commercial FPGAs. It does not require any additional specialized equipment, and thus, OPAL is a low-cost, flexible, and portable platform that can be controlled remotely. We demonstrate the feasibility, portability, and performance of OPAL by implementing it on Intel Arria 10 and Stratix 10 FPGA boards. We use OPAL to evaluate an open-source AES implementation for side-channel vulnerabilities.