The road towards aggressive pitch scaling with single exposure EUV

In 2015 IBM announced the first 7 nm test chip patterned with Extreme Ultraviolet Lithography (EUV) technology, enabling 36nm back end of the line (BEOL) metal pitch and self-aligned contact. Five years later, EUV has become the mainstream enabler for 7 nm node manufacturing, including the recent announcement of IBM Power10 high-performance chip. The high-performance definition of this technology, essential to IBMs server chips, has unique requirements that push the process complexity even further. In this paper, we will review some of the challenges and patterning solutions that will allow successful implementation of high-performance design definitions. We will also discuss our current efforts to extend the use of single expose EUV in the printing of interconnects to a second node, over a multi-patterning scheme, by replicating our strategy of co-optimization across all contributors to patterning success. We will review a few examples of this approach, including resolution improvements of our latest NXE3400 EUV system, all of which have allowed us to realize significant yields for our transistor interconnects at 28nm pitch. The entitlement of each process and material will be gauged through a robust characterization methodology that includes an understanding of the defect mode modulated, as well its ultimate correlation to electrical yield.