A Two-Step VCO-Based ADC with PWM Pre-coded Coarse Quantizer

This paper presents a new time-based ADC architecture that employs non-linearity cancellation and swing down scaling techniques to eliminate the non-idealities of the coarse and the fine VCO-based quantizers, respectively. The PWM pre-coded coarse quantizer allows for replacement of the DAC present in conventional two-step ADC architectures with simple logic gates and smoothing filters while relaxing the design constraints of the PWM pre-coded VCO based ADCs present in the literature. The entire power consumption of the ADC is 1.9mW under 1.2 V supply, while achieving an SNDR of 59 dB over 40 MHz bandwidth, yielding a conversion figure of merit of 33fJ/step.