Design and Implementation of FPGA Based Configurable AI Architecture with Deep Learning Algorithm

Abstract Our main aim is to design a reconfigurable FPGA architecture using Network on chip using deep learning which act as a validation algorithm. In the Existing System we were using WiNoC (wireless network on chip)which was not reconfigurable. The energy saving in existing model was 55% whereas the proposed model saves upto 83 % of energy. Within the projected system Deep Learning formula is developed in VLSI design with acceptable model is intended on FPGA SOC chip, by that performance are analysed in terms of error rate, regression rate, confusion rate.