Chapter Two - An efficient DVS scheme for on-chip networks.

Network-on-Chips (NoCs) consume a significant portion of multiprocessors' total power. Dynamic Voltage Scaling (DVS) which can reduce both static and dynamic power consumption is widely applied to NoCs. However, prior DVS schemes usually impose significant performance overhead to NoCs as NoCs need to work with lower clock frequencies when the supply voltage is scaled down. In this chapter, we propose a novel DVS scheme for NoCs with no performance overhead. We reduce power consumption when there is few Virtual Channels (VCs) that have active allocation requests at each cycle compared to the total number of available VCs. To enable multiple latencies with different slack times, we propose a new reconfigurable arbitration logic. In this method, we increase slack times to employ lower supply voltages for routers and accordingly, decrease the power consumption. We show that the proposed method can reduce power up to 45.7% over the baseline architecture without any performance degradation.