A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS

Peng Chen,Xi Meng,Jun Yin,Pui-In Mak,Rui P. Martins,Robert Bogdan Staszewski

IEEE Transactions on Circuits and Systems I: Regular Papers（2022）

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摘要

This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernier-TDC input range with little power overhead in order to overcome the stability issue in the conventional architectures. The hybrid TDC also facilitates a backgro...

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关键词

Oscillators,Phase locked loops,Jitter,Bandwidth,Circuit stability,Quantization (signal),Gain

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