10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV VMIN Reduction With Negligible Active Power Overhead

A 21-Mb/mm² SRAM design using 0.0367- $\mu {\mathrm{ m}}^{2}$ HCC bitcell on a 10-nm CMOS technology is presented. Gate-modulated self-collapse (GSC) write-assist is utilized to enable 175 mV $V_{\mathrm{ MIN}}$ reduction with negligible active energy overhead, and a modest 5.5% array area overhead on a 256-Kb instance. Compared to NBL and TVC write-assist techniques, GSC delivers comparable $V_{\mathrm{ MIN}}$ improvement across a wide frequency range with 31%–108% write energy reduction.