Graph Learning-Based Arithmetic Block Identification
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)(2021)
摘要
Arithmetic block identification in gate-level netlist is an essential procedure for malicious logic detection, functional verification, or macro-block optimization. We argue that existing methods suffer either scalability or performance issues. To address the problem, we propose a graph learning-based solution that promises to extract desired logic components from a complete design netlist. We fur...
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关键词
Representation learning,Sensitivity,Scalability,Wires,Logic gates,Graph neural networks,Task analysis
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