Continuous-Time MASH Architectures forWideband DSMs

BW = f s/(2 OSR). As this equation indicates, wideband ΣΔ ADCs having bandwidths in the hundreds of MHz require clock frequencies in the GHz range even to obtain a relatively low OSR of ten. In such low-OSR systems, MASH architectures achieve better power efficiency than traditional single-loop ΣΔ ADCs. Nanometer CMOS process technologies enable continuous-time ΣΔ ADCs operating at GHz clock frequencies. However, the combination of continuous-time and low-OSR at a GHz clock frequency presents new challenges. In this paper, ΣΔ ADCs including the traditional single-loop and MASH, are reviewed in the context of wideband wireless applications with out-of-band blockers. A unique circuit block in continuous-time MASH, a continuous-time residue generation circuit, is discussed in detail. Two wideband MASH implementations in a 28 nm CMOS process are compared and their properties and performances are discussed based on the architectural differences.