The Impacts of Ferroelectric and Interfacial Layer Thicknesses on Ferroelectric FET Design

Despite tremendous interests in ferroelectric field-effect transistors (FEFETs) for embedded, data-centric applications, the fundamental trade-offs between memory window (MW) and write voltage to optimize performance remains poorly understood. To that end, we fabricated ferroelectric (FE) ZrO ₂ based, p-type FEFETs and studied the impacts of FE and the interfacial oxide layer (IL) thicknesses ( t _FE and t _IL , respectively) on device performance. We observe that a decrease of t _FE and t _IL reduces not only write voltages for erasing and programming, but also the memory window. A quantitative analysis of these results offers the following insights and guidelines for FEFET design: to decrease write voltages, all of t _FE , t _IL and coercive field of FE needs to decrease, and to compensate for the subsequent decrease in MW, the polarization of the FE needs to be increased - notwithstanding the fact that the reliability implications of the magnitude of FE polarization still need to be understood.