Capacitance–resistance modeling of an inverter based on a nanoscale side-contacted field-effect diode with an overshoot suppression approach

Low-power and high-speed logic gates and memory cells based on side-contacted field-effect diodes (S-FED) exhibit considerably less overshoot and Miller-effect degradation compared to their CMOS counterparts. Numerical simulations of current and carrier densities during ON/OFF transitions are used to develop a rigorous model of internal capacitances and resistances inside the S-FED NOT gate. The model demonstrates that the value and location of internal capacitors and the role that they play in the ON and OFF states result in considerably less overshoot and input–output coupling. Suppression of overshoot and Miller effect can have a huge impact on reliability, bandwidth, crosstalk elimination, waveform integrity, and bandwidth in nanoscale electronics.