NOP-DH – Evaluation Over Bitonic Sort Algorithm

The growing use of Field Programmable Gate Array (FPGA) to increase application performance requires tools that simplify the digital circuit development process. Traditional approaches of Hardware Description Languages (HDLs) are complex and require specialized knowledge at a low-level abstraction. In turn, different approaches called High-Level Synthesis (HLS) aim at facilitating the development of FPGA applications, making this development process closer to those of software using programming languages such as C or C++. However, these alternatives do not properly exploit the parallelism capability of FPGAs as they are based on usual sequential approaches and, moreover, continue to depend on developer technical knowledge about the target hardware. The Notification Oriented Paradigm (NOP) emerges as an alternative to develop and execute applications. The NOP brings a new inference concept based on precise notifying collaborative entities. This type of inference allows presenting an innovative way of implicitly achieving decoupled and decentralized solutions, thereby enabling parallelism and distribution in a level of granularity as fine as possible in the envisaged computational platform. In this context, researches on NOP have proposed the design of digital circuits based on the NOP model, called NOP Digital Hardware (DH). In this paper, it is proposed to evaluate the use of the NOP-DH to develop the well-known Bitonic Sort, which is a sort algorithm useful as benchmark. This algorithm has particular properties that are advantageous for parallel execution, especially in FPGAs. Experiments were performed to compare the performance, amount of logic elements, and maximum frequency of NOP-DH against the traditional VHDL approach. These experiments demonstrated that even with a higher abstraction level of development, NOP-DH circuits achieve similar results when compared to the traditional development in VHDL.