Sub-Mu W Operation And Noise Reduction Of Monolithic 3-Axis Accelerometers Using A Sige-Mems-On-Cmos Technique

This paper reports the first demonstration of Ultra-Low-Power (ULP) operation below 1 mu W and noise reduction realized by a monolithic 3-axis accelerometer using a SiGe-MEMS-on-CMOS technique. In this work, the ULP operation is attributed to incorporating high-sensitivity SiGe-MEMS and low-power CMOS circuit with a monolithic configuration. The power consumption is confirmed to be 273 nW in an active mode and 160 nW in a standby mode. Furthermore, this work first evaluates the quantitative benefit of the monolithic configuration in view of noise reduction, and the result is a 30% lower noise density compared to a two-chip configuration using wire bonding, stemming from a 53% reduction of the parasitic capacitance. This work's approach enabling ULP operation and the noise reduction will contribute to the long battery life of sensors desired for IoT applications.