Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping

Coarse-grained reconfigurable architecture (CGRA) is a promising programmable device with high performance and power efficiency. The CGRA compilation problem is to map an application onto a 3D time-space model of CGRA. Adding the circuitry of synchronizers can relax the mapping constraint for data alignment in time; and thus, it significantly influences the compilation performance. However, data-departure synchronizers may be infeasible, because an output value may be used multiple times and has a high fan-out. Instead, data-arrival synchronizers can further improve performance and mappability of CGRAs with acceptable overhead, compared to the synchronization methods based on detour routing, register files, and FIFO. In this work, we design two kinds of data-arrival synchronizers and formulate them in an integer linear programming (ILP) based mapping approach. The separate ILP formulations of placement and routing speed up the architecture exploration with synchronizers by up to 3.03x. The experimental study shows that data-arrival synchronizers improve CGRA performance by 19.8% on average. The results of our quantitative study show that synchronizers also improve the mapping success rate by 1.91x on average. In conclusion, CGRAs with appropriate synchronizers have better mappability while using fewer resources.