A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS

Shiva Kiran,Ajay Balankutty,Yutao Liu,Rajeev Dokania, Hariprasath Venkataraman,Priya Wali,Stephen Kim,Yoel Krupnik,Ariel Cohen,Frank O'Mahony

2021 Symposium on VLSI Circuits（2021）

引用 6|浏览15

暂无评分

摘要

A receiver analog front end (AFE) suitable for a 224 Gb/s PAM-4 long-reach ADC-based SerDes receiver is implemented in Intel 10nm FinFET process. The AFE consists of distributed input matching network and a hybrid peaking CTLE followed by a VGA that drives an interleaved ADC used for characterization. The AFE achieves 19dB boost and 11.7dB peak gain at 54GHz while consuming 60mW.

查看译文

关键词

CMOS,receiver analog front end,AFE,Intel FinFET process,distributed input matching network,hybrid peaking CTLE,interleaved ADC,PAM-4 long-reach ADC-based SerDes receiver,VGA,size 10.0 nm,frequency 54.0 GHz,power 60.0 mW,frequency 56.0 GHz,gain 11.7 dB,gain 19 dB

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要