From Interconnect Materials and Processes to Chip Level Performance: Modeling and Design for Conventional and Exploratory Concepts

We survey latest device and interconnect scaling trends in literature and present an in-detail sensitivity analysis of advanced metallization and barrier/liner fabrication methods at a system level by evaluating representative designs using industry-standard electronic design tools. In particular, we look at the 7nm technology node and evaluate multiple process advancements for copper interconnects and vias and compare them with ruthenium wires and interconnects. Despite improvements to copper barrier/liner, vias, and geometry RC optimization, by utilizing system-level design metrics, we showcase that ruthenium is a viable option even at the 7nm node, sooner than projections made in literature, owing largely to the 5× improvement in ruthenium via resistance.