High-Speed LDPC Decoders Towards 1 Tb/s

IEEE Transactions on Circuits and Systems I: Regular Papers(2021)

引用 23|浏览9
暂无评分
摘要
Beyond 5G systems are expected to approach 1 Tb/s throughput. This poses a significant challenge to the channel decoder. In this paper, we propose a multi-core architecture based on full row parallel layered LDPC decoder with frame interleaving. Compared with conventional partially parallel layered architectures, the proposed architecture increases the throughput by applying frame interleaving int...
更多
查看译文
关键词
Parity check codes,Decoding,Throughput,Manganese,Parallel processing,Pipelines,Iterative decoding
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要