Semiconductor memory with MPIO of host Interface among processors

A multiple-path accessing semiconductor memory device provides interface function among the processors. The memory device can include the following components: a memory cell array which comprises a shared memory that is connected with two or a plurality of ports in operation, and the two or a plurality of ports can be independently accessed by two or a plurality of processors; an access path forming unit which is used to respond to the external signal exerted by the processor and form a data access path between one of the pots and the shared memory; and an interface unit which comprises a sign district and a mailbox district that can be accessed by the two or a plurality of processors in order to provide interface function to the communication among the two or a plurality of processors.