Complex Placement Region Handling Based on Electrostatic System Modeling

With the additional fence region constraints in modern circuit designs, the VLSI placement problem has become more complex and challenging. A placement solution without considering fence region constraints may cause many problems in the legalization stage and result in an inferior placement. In this paper, we present an effective placement region handling method based on the two-dimensional electrostatic system modeling. Under the fence region constrains, we first generate multiple density maps for assigning cells to their respective fence regions. Then, we further add proper fence filler nodes to each density map, which is able to squeeze fence cells to be placed closer. The placement performance is validated through experiments on ISPD 2015 benchmarks. Experimental results show that, compared with the state-of-the-art placer NTUplace4dr, our proposed method not only reduces the wirelength by 9.9% but also achieves 5x faster runtime.