A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing

This article demonstrates a 10-bit 500 MSPS segmented current steering digital to analog converter (CS-DAC), which is designed using CMOS 180 nm technology for wireless transmitter system. To obtain stringent linearity and high spurious-free dynamic range (SFDR) for such high speed and high-resolution DAC is the main design challenge. Considering this objective, the static and dynamic performances along with linearity of the DAC are improved using segmented architecture incorporating with CS-DAC structure. This segmented architecture negotiates between active area and high performance of the DAC. In this design, CS-DAC architecture maintains the 60% segmentation ratio, in which the 4-LSB bits are used in binary fashion and 3-LMSB bits along with 3-MSB input bits are utilized in unary structure. To improve the linearity and to mitigate the mismatch effect, an on-chip temperature and supply invariant voltage bias reference (VBR) circuit is proposed with hexa-decal biasing scheme. This technique minimizes the output glitches by reducing correlated noise generated from the bias cells. Using this architecture, the SFDR is calculated more than 77 dB up to near Nyquist input signal frequency of the 248.53 MHz. The CS-DAC consumes only 27.37 mW power at 18.06 MHz input frequency with 500 MSPS sampling rate.