Read-Out Architecture of CRYO System-on-Chip ASIC for Noble Liquid TPC Detectors.

This work presents the implementation of the digital read-out architecture of a System-On-Chip (SoC) optimized for Time Projection Chamber (TPC) detectors used in neutrino science. The CRYO ASIC works at cryogenic temperatures and performs signal pre-amplification, waveform digitization and channel multiplexing with minimum number of I/Os. The digital back-end is optimized to work with cryogenic liquids (LXe, 160 K and LAr, 87 K) providing data throughput up to 1 Gbps and can be programmed to maintain signal integrity up to 25 m cable length. Implemented in 130 nm CMOS process, the back-end architecture consists of a digital multiplexer, a custom 12b/14b encoder, a data serializer, and LVDS (Low-Voltage Differential Signaling) drivers with pre-emphasis enhancing techniques. The simulated output jitter of transmitter is 29.3 ps, peak-to-peak (0.15 UI) driving a 25 m cable at 1 Gbps data rate.