An Ion-to-Frequency ISFET Architecture for Ultra-Low Power Applications

This paper presents an Ion-to-Frequency ISFET architecture capable of operating at low power supplies, targeting fully-digital ultra-low power applications. The ISFET, biased in weak inversion, encodes the pH concentration as a frequency modulated digital signal by controlling the polarity and discharge rate of a capacitor. This architecture is implemented using digital gates operating at low voltages, achieving minimal power consumption and addressing the need for scalability to deep sub-micron technologies. Implemented in TSMC 0.18 mu m standard CMOS technology, each pixel occupies 20 mu m x 21 mu m and consumes a maximum of 33 pW operated at 0.2V while preserving a large sensitivity of 287 Hz/pH at a center frequency of 697Hz. Simulation results indicate low power consumption with a compact pixel size, becoming an efficient solution for the next-gen of portable and wearable applications.