A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead

Zheng Guo,Jami Wiedemer,Yusung Kim, Prithvee Sundararajan Ramamoorthy,Prateeksha Bindiganavile Sathyaprasad,Smita Shridharan,Daeyeon Kim,Eric Karl

2020 IEEE Symposium on VLSI Circuits（2020）

引用 2|浏览18

暂无评分

摘要

A 21Mb/mm ² SRAM design using 0.0367um ² HCC bitcell on a 10nm CMOS technology is presented. Gate-modulated self-collapse (GSC) write assist is utilized to enable 175mV reduction in V _MIN with minimal energy overhead. Instance area overhead is limited to 3-5% by implementing the GSC circuitry in a row-based configuration with modified SRAM bitcells.

查看译文

关键词

minimal energy overhead,instance area overhead,modified SRAM bitcells,10nm SRAM design,MIN reduction,negligible power overhead,SRAM design,10nm CMOS technology,HCC bitcell,gate-modulated self-collapse write assist,row-based configuration

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要