Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture

A multicarrier serial link receiver architecture allows for expanded symbol times to significantly relax the sampling clock jitter requirements that are currently imposing major limitations on achieving higher data rates. The proposed receiver utilizes a correlator-bank architecture with frequency channelization performed with down-conversion mixers, filters, and analog-to-digital converters (ADCs) for digitization. Continuous frequency-domain channel allocation is achieved with the utilization of digital inter-channel interference (ICI) cancellation. A detailed receiver noise analysis is presented and transient bit-error-rate simulations are utilized to evaluate the system performance with different modulation formats used on the multicarriers. Relative to a conventional four-level pulse amplitude modulation (PAM-4) system, the proposed receiver allows for a 3X improvement in jitter tolerance when operating at 64 Gb/s over a channel with 25 dB loss at 16 GHz.