High-Spurious-Harmonic-Rejection 32-53 GHz and 50-106 GHz Frequency Doublers using Digital Logic and DC Negative Feedback

We present two frequency doublers in 130 nm InP HBT technology. The doublers use digital logic and DC negative feedback to suppress unwanted harmonics. The single-ended output of the lower frequency doubler has -5 dBm output power over 32 GHz to 53 GHz output frequency range. First and third harmonic rejection is higher than 30 dBc. The delay control circuit with the feedback loop enables fourth harmonic rejection higher than 18 dBc. It consumes 0.94 W. The higher frequency doubler has -5 - -8 dBm single-ended output power over 50 to 106 GHz output frequency range with better than 25 dBc first harmonic rejection. It consumes 1.069 W.