An FPGA-Based Pentium (R) in a Complete Desktop System

Software simulation has been the predominant method for architects to evaluate microprocessor research proposals. There are three tenets in modeling new designs with software models: simulation speed, model accuracy and model completeness. The increasing complexity of the processor and accelerated trend to have multiple processors oil a chip are putting burden oil simulators to achieve all tenets mentioned, including accurately capturing OS effects. In this work we perform preliminary experimentation/prototyping with all emulation system which overcomes the tension to satisfy all three requirements. The system is an original Socket-7 based desktop processor system with typical hardware peripherals running modern operating systems such as Fedora Core 4 and Windows XP; however we have inserted a Xilinx Virtex-4 in place of the processor that, should sit in the motherboard and have used the Virtex-4 to host a complete version of the Pentium (R)(1) microprocessor (which consumes less than half its resources). We can therefore apply architectural changes to the processor and evaluate their effects oil the complete desktop system. We use this FPGA-based emulation system to conduct preliminary architectural experiments including growing the branch target buffer and the level I caches. In addition, we experimented with interfacing hardware accelerators such as DES and AES engines which resulted in 27x speedups.