Finite Element Stress Characterization of Stacked Die Package for Reliability Improvement and Architecture Optimization

Electronic products have been following light, thin, short, small as goals. In recent years, not only do these features have to provide more functionality and reliability. In response to this demand, many new processes such as wafer-level 7 nm euv and electronic packaging solutions have been developed in the market. Stacked wafer technology has been widely used in electronic packaging solutions in a variety of storage devices and electronic products. The accompanying problems and challenges continue to emerge, in which the delamination of the package failure mode leads to the inability of electronic products to operate as the biggest issue. This study is mainly to investigate the thermal stress behavior of the vertical stacking of chip bonds of wafer adhesives to reduce the thickness of the wafer in the stacked wafer structure to Improve package reliability by reducing the amount of deformation Utilize one-half symmetry model and adopt the reflow profile of JESD22-a113 (25 °C ~ 260 °C) As a basis and import into the ansys software for parametric development, Then use the Taguchi experiment method to configure the experimental parameters to explore the optimization parameters. Finally, the experimental results and the delamination results were verified by the Taguchi experiment method, and the stress shrinkage gradient model was introduced to find the next best potential factor for reducing the maximum stress, such as binder material Tg and Young's modulus compensation thermal expansion system. Observe the thermal stress behavior of stacked chips and help provide a reference for providing modified changes during development.