Linkage Control Policy on Area Pacesetter and Active Compensation for Chip Angle Correction

In order to improve the optical and electrical consistency in lighting and display, light emitting diode (LED) dies should be sorted and aligned precisely one by one. As per given current production process practices, the sorting efficiency is required to be more than 36 thousand units per hour (KUPH), while the alignment deviation should not exceed 1 mil (25.4 $\mu \text{m}$ ) and all dies’ angle deviations should fall within 5°. Among all the requirements, the chip angle correction is particularly difficult to achieve because a small die correction on wafer would cause a change in all dies’ positions, leading to significant performance degradation. This results in an ambiguity, due to the difficulty in balancing efficiency and accuracy. In this article, the influence factors of the accuracy deviation caused by the angle correction are analyzed in detail, and the negative effect caused by tiny deformation of the elastic substrate is studied with comprehensive experiments. The parallel scheduling mechanism of the angle correction is analyzed, and the influences on sorting performance are evaluated with stochastic petri net (SPN) model, so that the suitable working area is disclosed. A local compensation strategy using the local deformation trend of the membrane is utilized to optimize the accuracy of precorrection. Further, the alignment area is actively compensated according to the alignment precision requirements, so that the performance and accuracy requirements are balanced. In the chip packaging field, microchip angle correction is often needed. This method is applicable to similar situation and chips are adhesive on membrane.