Networks of the Tilera Multicore Processor

As a greater number of processor cores is integrated onto a single die, the design space for interconnecting these cores becomes more fertile. One manner to interconnect those cores is simply to mimic multichip multiprocessor computers of the past. Following the past, simple bus-based shared memory multiprocessors can be integrated onto a single piece of silicon. But, by following the past, we do not take advantage of the unique opportunities afforded by single-chip integration. Specifically, buses require global broadcast and do not scale to more than about 8 or 16 cores. Some multicore processors have used one-dimensional rings, but rings do not scale either because their bisection bandwidth does not increase as more cores as added. In this work we describe the architecture of iMesh, the mesh-based on-chip interconnection network of the Tile Processor. The Tile Processor is a tiled multicore architecture developed by Tilera Corporation, and is inspired by MIT’s Raw processor [333,317], which was the first tiled multicore processor. Tiled multicore architectures are Multiple Instruction Multiple Data (MIMD) machines consisting of a two-dimensional grid of general-purpose compute elements. The compute elements are called tiles or cores and are homogeneous. They are coupled together by packet-routed mesh interconnects, which provide the transport medium for off-chip memory access, Input/Output (I/O), interrupts, and other communication activity. Each tile in the Tile Processor is a powerful, full-featured computing system that can independently run an entire operating system, such as Linux. Likewise, multiple tiles can be used together …