Modeling and Optimization of Hybrid FinFET-Silicon Photonic Interconnects

Optical links have emerged as the best solution for short-reach communications (down to tens of meters), both in terms of speed and power consumption. In order to reduce energy-per-bit consumptions and enhance data rates, new technologies (for modulators, packaging, etc.) are being developed.Before implementing them into commercial products, it is essential to evaluate the impact of these new technologies on the overall performance of a link. In this work, a benchmarking tool is developed to optimize the design of electrical transceivers and to minimize the energy-per-bit consumption of a silicon photonic optical link integrated with CMOS FinFET transceivers. This tool is used to compare three stacking technologies (C4 bumps, micro-bumps and bump-less stacking) and evaluate their impacts on an optical link's data rate and power consumption. For this study, a silicon ring modulator is used to modulate the light from a laser, and all components of the link are designed such that a bit-error-rate of $ 10^{-12}$ is achieved. This work shows that replacing conventional C4 bumps by a bump-less stacking interface extends the bandwidth of an optical link from 45 Gbps to 65 Gbps, and reduces the energy-per-bit consumption from 2 pJ/bit to 0.6 pJ/bit at 45 Gbps.