A Systematic Transaction-level Modeling and Verification

Design flow by transaction-level (TL) prototyping has received a great deal of attention as a solution of systemon-chip challenges that cannot be addressed by traditional design methodologies. This work is to address the issue of systematic TL modeling and verification methods. Specifically, (1) A systematic design modeling flow with a set of well-defined transaction protocols and TL model verification method are proposed; (2) We show comprehensive details on architecture (bus, memory, basic blocks) exploration results obtained by using our TL modeling and verification methodology for movie capture application, which interwinds Camera I/F, two DMAs, LCD buffer, SDRAM, and MPEEG HW accelerator.