Pulse Pattern Generator and sets in 65-nm CMOS

Fully-integrated 40-Gb/s pulse p (PPG) and bit-error-rate tester (BERT) ch presented in 65-nm CMOS technology. Usin inputs, the PPG and BERT achieve full opera wide data range from 40 Mb/s to 40 Gb/s. B CDR circuits are also included to provide standard specification testing.