Hw \ sw implementation of iris recognition algorithm in the fpga

Recent years have seen the growth of new pattern recognition applications which based on personal biometric characteristics. These applications are used for security, logical or physical access control, etc. Iris recognition has been successfully deployed in several large-scale public applications. In this paper, three different methods are proposed to accelerate the simulation of biometric systems based on iris recognition with performance analysis. The whole iris recognition algorithm has been implemented in Cyclone II FPGA achieving significant reduction in execution time when compared with software implementation .The results show that with a clock speed of 50MHZ from image of 640*480, the gain in best method in the time execution is just 33% and the total time need by a software solution running on the same embedded microprocessor in the architecture.