Compact Code-Based Signature for Reconfigurable Devices With Side Channel Resilience

In this paper, we present a compact design for the code based signature called LEDAsig with side channel resistance. Existing implementations concentrate on the high-speed feature while few of them have considerations on area or power efficiency which are particularly decisive for low-cost or power constrained IoT applications. We propose an area-efficient FPGA architecture for systematically rotating the QC-LDGM codes amongst the block RAMs with read-first mode. Additionally, the side channel vulnerability of LEDAsig is carefully examined, and protective masking schemes are introduced accordingly to safeguard our design from power analysis attacks. Effectiveness of these schemes is verified on SAKURA-G FPGA board. Up till now, the design presented in this work is the most compact one and also the first side-channel secure one addressing first-order and (univariate) second-order differential power analysis for the code based signature schemes in the open literature. We show for instance that our first-order (second-order) protected implementation can sign a signature in 117 (203) ms on a Xilinx Spartan-6 FPGA, occupying only 622 (1142) slices, and therefore is a prospective candidate for post-quantum signature schemes in low-resource settings.