A 1.64mW Differential Super Source-Follower Buffer with 9.7GHz BW and 43dB PSRR for Time-Interleaved ADC Applications in 10nm

A differential buffer for high bandwidth (BW), Time-Interleaved Analog to Digital Converters (TI ADCs) is described. The buffer, nested between Track and Hold (TH) circuits, drives the ADC input signal to the individual sub ADCs. A differential, super source-follower based architecture is utilized in the buffer. This architecture features high power supply rejection ratio (PSRR) together with high BW, low power consumption and low Inter-Symbol Interference (ISI). The buffer was fabricated in 10nm Intel process as a part of a 112Gb/s SerDes receiver. A unique method was developed to accurately measure the buffer's output waveform. Measurements show a BW of 9.7GHz, PSRR of 43dB and power consumption of 1.64mW, which is a 68% power reduction compared to the prior art.