Proactive Row Buffer Management for LPDDR2-NVM Devices

LPDDR2-NVM has been announced as an industry standard to efficiently interface the emerging non-volatile memory devices such as phase change memory (PCM). This standard interface has been adopted in most commercial PCM devices. However, existing PCM research has less addressed or overlooked this standard interface under assumption that it is similar to conventional DRAM interface. Unlike the conventional DRAM interface, the row buffer architecture specified in LPDDR2-NVM has several unique features in order to support the different characteristics of PCM operation. In this paper, we devise a proactive row buffer management for enhancing the performance with almost negligible implementation overhead, targeting LPDDR2-NVM compatible memory devices. Our extensive simulations demonstrate 12.2% performance enhancement and 0.3% energy reduction of memory system, on average, with fairly small cost overheads.