Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators

We present two technology portable design techniques to achieve zero steady-state output voltage ripple in digital LDOs. Traditional digital LDOs have an inherent output voltage ripple due to the limit cycle oscillations at a frequency of F-clock/(2 x Mode). We use a 4-bit digital LDO as the test vehicle to investigate these two new techniques. The power-switch bank consists of PMOS HVT (high threshold) devices. The first method uses body biasing of the switches via an auxiliary analog loop to minimize the ripple voltage. Effectively, the analog loop enables the power switches to carry the extra ripple current and has little impact on the efficiency. In the second method, zero steady-state ripple is achieved by modulating the gate-driver voltage-swings at the power-switch gate. In both the techniques, when the digital LDO is in steady state, the analog loop only carries the ripple current magnitude. Control from the analog and digital loops are ping-ponged based on load transients. The LDO design handles inputs from 0.5-1.5V and supports a 0.4-1.2V output voltage for a load range of 0.1-to-20mA (200X). The LDO achieves 99.4% current efficiency and near-zero output voltage ripple. The total area of chip is 0.08mm(2) in TSMC 65nm CMOS GP.