SUPPRESSION OF IMD3 IN CMOS POWER AMPLIFIER USING BIAS CIRCUIT OF COMMON-GATE TRANSISTOR WITH CASCODE STRUCTURE

In this study, we propose a technique to improve the linearity of complementary metal-oxide semiconductor (CMOS) power amplifiers with a cascode structure. From the investigation of the influence of the impedance of an envelope signal on the linearity, we find that the load impedance of the envelope signal of the common-source transistor should be reduced. To obtain alow load impedance of the envelope signal, we reduce the value of the gate resistor of the common-gate transistor. After investigating the influences of the value of the resistance on the third-order intermodulation distortion (IMD3), we extract the optimum value of the resistance. We also consider the electrostatic discharge protection issue and the effects of the variations in the parasitic components of bond-wires, in the process of the extraction of the optimum value. To verify the feasibility of the optimization technique of the resistance of the bias circuit of the common-gate transistor of the amplifier, we design a power amplifier using a 180-nm RFCMOS process for wireless local area network (WLAN) 802.11n applications. We obtain the measured maximum linear output power of 22.2 dBm with a 26.7% power-added efficiency and a 3.72% error vector magnitude. We use an 802.11n modulated signal with 64-QAM (MCS7) at 65Mb/s. From the measured results, we successfully verify the feasibility of the proposed optimization technique of the resistance of the bias circuit of the common-gate transistor.