Designing energy-efficient imprecise adders with multi-bit approximation

Since early 2000s, achieving significant energy-efficiency for CMOS VLSI circuit design has become more difficult. Approximate computing is a hopeful solution for enhancing power-efficiency in error-tolerant applications. In such systems, adders play an essential role and mainly contribute to the system's total power and area consumption. Many proposals have been introduced in the literature that build large adders while using novel low power full adder structure as its building blocks. However, single-bit structure approximation, only limits the design space of approximate adders. And leads to a poor trade-off between accuracy and power dissipation. This paper proposes a novel approach for design of multi-bit adders, based on three novel approximate 2-bit adder circuits. Simulation results demonstrates that the proposed adders consume less area and power than the state-of-the-art approximate adders. Up to 80% power improvements are attainable for the proposed designs as compared with the baseline adders.