Comparative Design of NMOS and PMOS Capacitor-less Low Dropout Voltage Regulators (LDOs) Suited for SoC Applications

In this paper, two architectures of Low Dropout Voltage Regulator (LDO) using NMOS and PMOS pass transistors is designed and implemented using 130nm CMOS technology. The performance of the two designs is compared while using the same quiescent current, input voltage, output voltage, and compensation capacitors. The two architectures can provide output voltage of 1V from a 1.2V supply voltage and support output current from 30μA to 100mA while consuming a quiescent current of 6μA. Both LDOs can support a range of loading capacitor 0–50pF. The NMOS LDO is designed with an auxiliary charge pump (CP) to step up input voltage of 1.2V to 2V, thus three architectures of CPs are discussed, designed, and optimized to provide a stable 5μA using a 1MHz of switching frequency. The cross-coupled CP is chosen to be the auxiliary CP because it consumed the smallest silicon area. Both LDOs are fully integrated and consume low power so that it can be used in SoCs. The PVT simulations are implemented to ensure the reliability of the design, also the specifications are compared to other techniques reported previously.