A 0.65 V, linearized cascade UWB LNA by application of modified derivative superposition technique in 130 nm CMOS technology

In this paper, a low-voltage linearized ultra-wideband (UWB) low noise amplifier (LNA) is presented. The core of the proposed circuit is a two-stage cascade structure which is forward body biased to operate under a low supply voltage. In the proposed topology the low linearity drawback of the cascade structure is improved by exploiting the modified derivative superposition (MDS) technique at the second stage. The MDS technique consists of an auxiliary transistor biased in the moderate inversion region paralleled with the main transistor biased in the strong inversion region and two degeneration inductors connected at the source node of the main and auxiliary transistors which altogether aim to cancel out contributions of both the second and third-order non-linearity coefficients on the third-order input intercept point ( IIP 3 ). Applying MDS technique on cascade structure has the advantage to have both high linearity and low supply voltage features in an UWB LNA. Simulated at post-layout level in 130 nm RFCMOS TSMC technology, the structure features a 13.8 dBm IIP 3 , consuming only 11.2 mW from a low supply voltage of 0.65 V. The proposed LNA achieves a relatively flat gain of 12 ± 1 dB, noise figure of 1.8–4 dB, and return power loss less than − 10 dB.