Suppressing Methods of Parasitic Capacitance Caused Interference in a SiC MOSFET Integrated Power Module

By integrating gate drivers in the silicon carbide (SiC) power module, low parasitic inductances in power loop and driving loop are realized to improve switching performance. However, the voltage variation of midpoint in the half-bridge module causes interference at the input of gate drivers. The interference loop is analyzed in this paper, considering corresponding parameters, such as parasitic capacitance and switching speed. A circuit model is derived with experimental verification. Based on the circuit model and analysis, discussions of this interference are done and it shows that serious situations such as shoot-through may happen. Therefore, different suppressing methods of this parasitic capacitance caused interference are proposed in this paper and comparison between these techniques is done, showing that the shielding method can totally eliminate this interference. This paper offers help for the design and fabrication of SiC power module with integrated gate drivers.