Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder.

IEEE Journal on Emerging and Selected Topics in Circuits and Systems(2018)

引用 27|浏览32
暂无评分
摘要
This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry Cut-Back Adder (CCBA), in whic...
更多
查看译文
关键词
Adders,Low power electronics,Digital circuits,Timing,Optimization
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要