Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems(2018)
摘要
This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry Cut-Back Adder (CCBA), in whic...
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关键词
Adders,Low power electronics,Digital circuits,Timing,Optimization
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